SH7280 Datasheet, PDF (920/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 18 Synchronous Serial Communication Unit (SSU)
Initial
Bit
Bit Name Value R/W
Description
3
TEIE
0
R/W
Transmit End Interrupt Enable
When this bit is set to 1, an SSTEI interrupt request is
enabled.
2
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, an SSTXI interrupt request is
enabled.
1
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, an SSRXI interrupt request
and an SSOEI interrupt request are enabled.
0
CEIE
0
R/W
Conflict Error Interrupt Enable
When this bit is set to 1, an SSCEI interrupt request is
enabled.
Rev. 1.00 Jun. 26, 2008 Page 890 of 1692
REJ09B0393-0100