SH7280 Datasheet, PDF (1713/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Index
Numerics
16-bit/32-bit displacement ........................ 33
A
A/D conversion time............................... 999
A/D converter (ADC) ............................. 971
A/D converter activation......................... 618
A/D converter activation by MTU2
and MTU2S .......................................... 1000
A/D converter characteristics................ 1651
A/D converter start request delaying
function................................................... 599
A/D trigger input timing ....................... 1646
Absolute accuracy................................. 1005
Absolute address....................................... 33
Absolute address accessing....................... 33
Absolute maximum ratings................... 1591
AC characteristics................................. 1596
AC characteristics measurement
conditions ............................................. 1650
Access size and data alignment .............. 305
Access wait control................................. 315
Address errors......................................... 105
Address map ........................................... 250
Address multiplexing.............................. 325
Addressing modes..................................... 34
Arithmetic operation instructions ............. 52
Auto-refreshing....................................... 346
Auto-request mode ................................. 411
B
Banked register and input/output
of banks .................................................. 156
Bit manipulation instructions.................... 60
Bit synchronous circuit ........................... 965
Block transfer mode ................................ 225
Boot mode............................................. 1417
Branch instructions ................................... 57
Break detection and processing....... 815, 877
Break on data access cycle...................... 191
Break on instruction fetch cycle.............. 190
Burst mode.............................................. 424
Burst ROM (clock asynchronous)
interface .................................................. 359
Burst ROM (clock synchronous)
interface .................................................. 367
Bus arbitration......................................... 375
Bus state controller (BSC) ...................... 245
Bus timing............................................. 1603
Bus-released state...................................... 62
C
Calculating exception handling
vector table addresses ............................. 100
CAN interface ....................................... 1021
CAN sleep mode ................................... 1063
Cascaded operation ................................. 534
Caution on period setting ........................ 634
Chain transfer.......................................... 226
Changing the frequency .......................... 745
Clock frequency control circuit................. 75
Clock operating modes ............................. 78
Clock pulse generator (CPG) .................... 73
Clock synchronous mode ................ 751, 796
Clock timing ......................................... 1597
Clocked synchronous serial format......... 954
CMCNT count timing ............................. 729
Compare match timer (CMT) ................. 723
Complementary PWM mode .................. 554
Conflict between byte-write
and count-up processes of CMCNT........ 734
Rev. 1.00 Jun. 26, 2008 Page 1683 of 1692
REJ09B0393-0100