SH7280 Datasheet, PDF (125/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 5 Exception Handling
Section 5 Exception Handling
5.1 Overview
5.1.1 Types of Exception Handling and Priority
Exception handling is started by sources, such as resets, address errors, register bank errors,
interrupts, and instructions. Table 5.1 shows their priorities. When several exception handling
sources occur at once, they are processed according to the priority shown.
Table 5.1 Types of Exception Handling and Priority Order
Type
Reset
Address
error
Instruction
Register
bank error
Interrupt
Exception Handling
Power-on reset
Manual reset
CPU address error
DMAC address error
Integer division exception (division by zero)
Integer division exception (overflow)
Bank underflow
Bank overflow
NMI
User break
H-UDI
IRQ
On-chip peripheral modules A/D converter (ADC)
Controller area network (RCAN-ET)
Direct memory access controller (DMAC)
Compare match timer (CMT)
Bus state controller (BSC)
Watchdog timer (WDT)
USB function module (USB) DTC transfer
end
Multi-function timer pulse unit 2 (MTU2)
Priority
High
Low
Rev. 1.00 Jun. 26, 2008 Page 95 of 1692
REJ09B0393-0100