SH7280 Datasheet, PDF (953/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 18 Synchronous Serial Communication Unit (SSU)
18.5 SSU Interrupt Sources and DTC or DMAC
The SSU interrupt requests are an overrun error, a conflict error, a receive data register full,
transmit data register empty, and a transmit end interrupts. Of these interrupt sources, a receive
data register full, and a transmit data register empty can activate the DTC or DMAC for data
transfer.
Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector
address, and both a transmit data register empty and a transmit end interrupts are allocated to the
SSTXI vector address, the interrupt source should be decided by their flags. Table 18.8 lists the
interrupt sources.
When an interrupt condition shown in table 18.8 is satisfied, an interrupt is requested. Clear the
interrupt source by CPU, DTC, or DMAC data transfer.
Table 18.8 SSU Interrupt Sources
Abbreviation Interrupt Source
Symbol Interrupt Condition
DTC or DMAC
Activation
SSERI
Overrun error
SSOEI (RIE = 1) • (ORER = 1) 
Conflict error
SSCEI (CEIE = 1) • (CE = 1) 
SSRXI
Receive data register full SSRXI (RIE = 1) • (RDRF = 1) Yes
SSTXI
Transmit data register empty SSTXI (TIE = 1) • (TDRE = 1) Yes
Transmit end
SSTEI (TEIE = 1) • (TEND = 1) 
Rev. 1.00 Jun. 26, 2008 Page 923 of 1692
REJ09B0393-0100