SH7280 Datasheet, PDF (110/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 4 Clock Pulse Generator (CPG)
PLL
FRQCR/MCLKCR/ACLKCR
Multipli-
Division Ratio Setting
cation
Ratio Iφ Bφ Pφ Mφ Aφ Iφ
Clock Ratio
Clock Frequency (MHz)*
Bφ Pφ Mφ Aφ Input Clock Iφ Bφ Pφ Mφ Aφ
×8
1/1 1/2 1/4 1/4 1/4 8 4 2 2 2 12.5
100 50 25 25 25
1/1 1/2 1/4 1/2 1/4 8 4 2 4 2
100 50 25 50 25
1/1 1/2 1/4 1/2 1/2 8 4 2 4 4
100 50 25 50 50
1/1 1/2 1/4 1/1 1/4 8 4 2 8 2
100 50 25 100 25
1/1 1/2 1/4 1/1 1/2 8 4 2 8 4
100 50 25 100 50
1/1 1/2 1/2 1/2 1/2 8 4 4 4 4
100 50 50 50 50
1/1 1/2 1/2 1/1 1/2 8 4 4 8 4
100 50 50 100 50
Notes:
* Clock frequencies when the input clock frequency is assumed to be the shown value.
1. The PLL multiplication ratio is fixed at ×8. The division ratio can be selected from ×1, ×1/2, ×1/4,
and ×1/8 for each clock by the setting in the frequency control register.
2. The output frequency of the PLL circuit is obtained by multiplication of the frequency of the input
from the crystal resonator or EXTAL pin and the multiplication ratio (×8) of the PLL circuit. This
output frequency must be 100 MHz or lower.
3. The input to the divider is always the output from the PLL circuit.
4. The internal clock (Iφ) frequency is obtained by multiplication of the frequency of the input from the
crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio
of the divider. The resultant frequency of the internal clock (Iφ) must not exceed 100 MHz
(maximum operating frequency) or lower.
5. The bus clock (Bφ) frequency is obtained by multiplication of the frequency of the input from the
crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio
of the divider. The resultant frequency of the bus clock (Bφ) must not exceed 50 MHz or the
internal clock (Iφ) frequency.
6. The peripheral clock (Pφ) frequency is obtained by multiplication of the frequency of the input from
the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division
ratio of the divider. The resultant frequency of the peripheral clock (Pφ) must not exceed 50 MHz or
the bus clock (Bφ) frequency.
7. When using the MTU2S, the MTU2S clock (Mφ) frequency must not exceed the internal clock (Iφ)
frequency. The MTU2S clock (Mφ) frequency is obtained by multiplication of the frequency of the
input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and
the division ratio of the divider.
8. The frequency of the CK pin output is always equal to the bus clock (Bφ) frequency.
9. When using the AD, the AD clock (Aφ) frequency must be equal to or higher than the peripheral
clock (Pφ) frequency.
10. When using the USB, the peripheral clock (Pφ) frequency must be 13 MHz or higher.
11. Uφ must be fixed to 48 MHz. When generating Uφ from the divider, input the clock 12 MHz or
connect the crystal resonator of 12MHz to the EXTAL or XTAL.
Rev. 1.00 Jun. 26, 2008 Page 80 of 1692
REJ09B0393-0100