SH7280 Datasheet, PDF (365/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
(4) Single Read
A read access ends in one cycle when the data bus width is larger than or equal to the access size.
This, simply stated, is single read. As the SDRAM is set to the burst read with the burst length 1,
only the required data is output. A read access that ends in one cycle is called single read.
Figure 9.19 shows the single read basic timing.
CK
A25 to A0
A12/A11*¹
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*²
Tr
Tc1
Td1
Tde (Tap)
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.19 Basic Timing for Single Read (CAS Latency 1, Auto-Precharge)
Rev. 1.00 Jun. 26, 2008 Page 335 of 1692
REJ09B0393-0100