SH7280 Datasheet, PDF (208/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 7 User Break Controller (UBC)
7.3.8 Break Address Mask Register_2 (BAMR_2)
BAMR_2 is a 32-bit readable/writable register. BAMR_2 specifies bits masked in the break
address bits specified by BAR_2. BAMR_2 is initialized to H'00000000 by a power-on reset, but
retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BAM2_31 BAM2_30 BAM2_29 BAM2_28 BAM2_27 BAM2_26 BAM2_25 BAM2_24 BAM2_23 BAM2_22 BAM2_21 BAM2_20 BAM2_19 BAM2_18 BAM2_17 BAM2_16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BAM2_15 BAM2_14 BAM2_13 BAM2_12 BAM2_11 BAM2_10 BAM2_9 BAM2_8 BAM2_7 BAM2_6 BAM2_5 BAM2_4 BAM2_3 BAM2_2 BAM2_1 BAM2_0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Bit Name
Initial
Value
BAM2_31 to All 0
BAM2_0
Note: n = 31 to 0
R/W Description
R/W Break Address Mask 2
Specify bits masked in the channel-2 break address
bits specified by BAR_2 (BA2_31 to BA2_0).
0: Break address bit BA2_n is included in the break
condition
1: Break address bit BA2_n is masked and not
included in the break condition
Rev. 1.00 Jun. 26, 2008 Page 178 of 1692
REJ09B0393-0100