SH7280 Datasheet, PDF (1638/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 31 Electrical Characteristics
CK
A25 to A0
CSn
RD/WR
Read
RD
D31 to D0
Write
WEn
D31 to D0
BS
DACKn
TENDn*
WAIT
T1
t_AD1
t_AS
t_CSD1
t_RWD1
tRSD
TwX
t_WED1
t_WDD1
t_BSD
t_BSD
t_DACD
t_WTH
t_WTS
t_WTH
tWTS
T2
t_AD1
t_CSD1
t_RWD1
t_RSD
t_AH
t_RDS1
t_RDH1
tWED1
t_AH
t_WDH1
t_DACD
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 31.13 Basic Bus Timing for Normal Space (One External Wait Cycle)
Rev. 1.00 Jun. 26, 2008 Page 1608 of 1692
REJ09B0393-0100