SH7280 Datasheet, PDF (780/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 15 Watchdog Timer (WDT)
15.5.4 Manual Reset in Watchdog Timer Mode
When a manual reset occurs in watchdog timer mode, the bus cycle is continued. If a manual reset
occurs while the bus is released or during DMAC burst transfer, manual reset exception handling
will be pended until the CPU acquires the bus mastership.
However, if the duration from generation of the manual reset to the bus cycle end is equal to or
longer than the duration of the internal manual reset activated, the occurrence of the internal
manual reset source is ignored instead of being pended, and the manual reset exception handling is
not executed.
Rev. 1.00 Jun. 26, 2008 Page 750 of 1692
REJ09B0393-0100