SH7280 Datasheet, PDF(276/1726 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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SH7280 Datasheet, PDF (276/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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Section 9 Bus State Controller (BSC)

6. SRAM interface with byte selection

ï£§ Can connect directly to a SRAM with byte selection.

7. Burst ROM interface (clock synchronous)

ï£§ Can connect directly to a ROM of the clock-synchronous type.

8. Bus arbitration

ï£§ Shares all of the resources with other CPU and outputs the bus enable after receiving the

bus request from external devices.

9. Refresh function

ï£§ Supports the auto-refresh and self-refresh functions.

ï£§ Specifies the refresh interval using the refresh counter and clock selection.

ï£§ Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8).

10. Usage as interval timer for refresh counter

ï£§ Generates an interrupt request at compare match.

Figure 9.1 shows a block diagram of the BSC.

Rev. 1.00 Jun. 26, 2008 Page 246 of 1692

REJ09B0393-0100

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