SH7280 Datasheet, PDF (461/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 10 Direct Memory Access Controller (DMAC)
10.5 Usage Notes
10.5.1 Setting of the Half-End Flag and the Half-End Interrupt
Since the following points for caution apply in cases where reference to the state of the half-end
flag in the CHCR register or the half-end interrupt is used in conjunction with the reload function,
please take care on these points.
Ensure that the reloaded number of transfers (the value set in RDMATCR) is always the same as
the number of transfers that was initially set (the value set in DMATCR). If the initial setting in
DMATCR and the value for the second and later transfers in RDMATCR are different, the timing
with which the half-end flag is set may be faster than half the number of transfers, or the half-end
flag might not be set at all. The same considerations apply to the half-end interrupt.
10.5.2 Timing of DACK and TEND Outputs
When the external memory is MPX-I/O or burst MPX-I/O, assertion of the DACK output has the
same timing as the data cycle. For details, see the respective figures under section 9.5.5, MPX-I/O
Interface, in section 9, Bus State Controller.
When the memory is other than the MPX-I/O or burst MPX-I/O, the DACK output is asserted
with the same timing as the corresponding CS signal.
The TEND output does not depend on the type of memory and is always asserted with the same
timing as the corresponding CS signal.
Rev. 1.00 Jun. 26, 2008 Page 431 of 1692
REJ09B0393-0100