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| SH7280 Datasheet, PDF (367/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family | |||
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Section 9 Bus State Controller (BSC)
CK
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*2
Tr
Tc1
Tc2
Tc3
Tc4 Trwl
Tap
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.20 Basic Timing for Burst Write (Auto-Precharge)
Rev. 1.00 Jun. 26, 2008 Page 337 of 1692
REJ09B0393-0100
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