SH7280 Datasheet, PDF (909/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 17 Serial Communication Interface with FIFO (SCIF)
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
M = (0.5 − ¹ ) − (L − 0.5) F − ^{D − 0.5} (1 + F) × 100 %
2N
N
Where: M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2.
Equation 2:
When D = 0.5 and F = 0:
M = (0.5 − 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
17.6.7 FER Flag and PER Flag of Serial Status Register (SCFSR)
The FER flag and PER flag in the serial status register (SCFSR) are status flag that apply to next
entry to be read from the receive FIFO data register (SCFRDR). After the CPU or DMAC reads
the receive FIFO data register, the flags of framing errors and parity errors will disappear.
To check the received data for the states of framing errors and parity errors, only read the receive
FIFO register after reading the serial status register.
Rev. 1.00 Jun. 26, 2008 Page 879 of 1692
REJ09B0393-0100