SH7280 Datasheet, PDF (1017/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 20 A/D Converter (ADC)
20.4.1 Single-Cycle Scan Mode
The following example shows the operation when analog input channels 0 to 3 (AN0 to AN3) are
selected and the A/D conversion is performed in single-cycle scan mode using four channels.
1. Set the ADCS bit in the A/D control register (ADCR) to 0.
2. Set all bits ANS0 to ANS3 in the A/D analog input channel select register (ADANSR) to 1.
3. Set the OFC and SH bits in the A/D bypass control register_0 (ADBYPSCR_0).
4. Set the ADST bit in the A/D control register (ADCR) to 1 to start A/D conversion.
5. After channels 0 to 2 (GrA) are sampled simultaneously, offset canceling processing (OFC) is
performed*. Then, A/D conversion is performed on channel 0. Upon completion of the A/D
conversion, the A/D conversion result is transferred to ADDR1. In the same way, channel 2 is
converted and the A/D conversion result is transferred to ADDR2.
6. A/D conversion of channel 3 is then started. Upon completion of the A/D conversion, the A/D
conversion result is transferred to ADDR3.
7. When A/D conversion ends on all specified channels (AN0 to AN3), the ADF bit is set to 1,
the ADST bit is automatically cleared to 0, and the A/D conversion ends. At this time, if the
ADIE bit is set to 1, an ADI interrupt is generated after the A/D conversion.
Note: * The operation depends on the OFC and SH bit settings in ADBYPSCR_0. For details,
see figures 20.2 through 20.5.
Rev. 1.00 Jun. 26, 2008 Page 987 of 1692
REJ09B0393-0100