SH7065 Datasheet, PDF (98/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Instruction
Instruction Code Operation
STS
DSR,Rn
0000nnnn01101010 DSR → Rn
STS
A0,Rn
0000nnnn01111010 A0 → Rn
STS
X0,Rn
0000nnnn10001010 X0 → Rn
STS
X1,Rn
0000nnnn10011010 X1 → Rn
STS
Y0,Rn
0000nnnn10101010 Y0 → Rn
STS
Y1,Rn
0000nnnn10111010 Y1 → Rn
STS.L MACH,@-Rn 0100nnnn00000010 Rn – 4 → Rn, MACH → (Rn)
STS.L MACL,@-Rn 0100nnnn00010010 Rn – 4 → Rn, MACL → (Rn)
STS.L PR,@-Rn 0100nnnn00100010 Rn – 4 → Rn, PR → (Rn)
STS.L DSR,@-Rn 0100nnnn01100010 Rn – 4 → Rn, DSR → (Rn)
STS.L A0,@-Rn
0100nnnn01110010 Rn – 4 → Rn, A0 → (Rn)
STS.L X0,@-Rn
0100nnnn10000010 Rn – 4 → Rn, X0 → (Rn)
STS.L X1,@-Rn
0100nnnn10010010 Rn – 4 → Rn, X1 → (Rn)
STS.L Y0,@-Rn
0100nnnn10100010 Rn – 4 → Rn, Y0 → (Rn)
STS.L Y1,@-Rn
0100nnnn10110010 Rn – 4 → Rn, Y1 → (Rn)
TRAPA #imm
11000011iiiiiiii PC/SR → stack area,
(imm × 4 + VBR) → PC
Note: * Number of states until transition to sleep state.
Execution
States T Bit
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
8
—
Caution:
• The table shows the minimum number of execution states. In practice, the number of
instruction execution states will be increased in cases such as the following:
 When there is conflict between an instruction fetch and a data access
 When the destination register of a load instruction (memory → register) is also used by the
following instruction
 When the branch destination address of a branch instruction is address 4n + 2
 Depending on the number of cycles of the instruction fetch destination or data access
destination (see 8.4, Number of Access Cycles (SH7065A) in section 8, Bus State
Controller (BSC), for details).
Rev. 5.00 Sep 11, 2006 page 76 of 916
REJ09B0332-0500