SH7065 Datasheet, PDF (844/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 22 Electrical Characteristics
22.3.9 Watchdog Timer Timing
Table 22.12 Watchdog Timer Timing
Conditions: V_CC = PLLV_CC = 3.0 to 3.6 V, AV_CC = 3.0 to 3.6 V, AV_CC = V_CC ±10%,
V_SS = PLLV_SS = PV_SS = AV_SS = 0 V, Ta = –20 to +75°C
Item
WDTOVF delay time
Symbol Min
tWOVD
—
Max
Unit Figure
100
ns
Figure 22.31
Mφ
WDTOVF
t_WOVD
t_WOVD
Figure 22.31 Watchdog Timer Timing
22.3.10 Serial Communication Interface Timing
Table 22.13 Serial Communication Interface Timing
Conditions: V_CC = PLLV_CC = 3.0 to 3.6 V, AV_CC = 3.0 to 3.6 V, AV_CC = V_CC ±10%,
V_SS = PLLV_SS = PV_SS = AV_SS = 0 V, Ta = –20 to +75°C
Item
Symbol Min
Max
Unit Figure
Input clock cycle
Input clock cycle (synchronous)
tscyc
4
tscyc
6
—
Pφ
Figure 22.32,
—
Pφ
Figure 22.33
Input clock pulse width
tsckw
0.4
0.6
tscyc
Input clock rise time
tsckr
—
1.5
Pφ
Input clock fall time
tsckf
—
1.5
Pφ
Transmit data delay time (synchronous) tTXD
—
100
ns
Figure 22.33
Receive data setup time (synchronous)
tRXS
100
—
ns
Receive data hold time (synchronous)
tRXH
100
—
ns
Note: When the SCI output pin is set as an open-drain output, the characteristics depend on the
pull-up resistance.
Rev. 5.00 Sep 11, 2006 page 822 of 916
REJ09B0332-0500