SH7065 Datasheet, PDF (756/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 19 256 kB Flash Memory (F-ZTAT)
19.4 Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 19.3.
Table 19.3 Flash Memory Registers
Register Name
Abbreviation R/W
Initial
Value
Address
Access
Size
Flash memory control register 1 FLMCR1
R/W^*1 H'00^*2
FFFF0800 8
Flash memory control register 2
Erase block register 1
Erase block register 2
FLMCR2
EBR1
EBR2
R
R/W^*1
R/W^*1
H'00
H'00^*3
H'00^*3
FFFF0801 8
FFFF0802 8
FFFF0803 8
RAM emulation register
RAMER
R/W
H'0000 FFFF0C70 8, 16, 32
Notes: FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers, and RAMER is a 16-bit register.
Only byte accesses are valid for FLMCR1, FLMCR2, EBR1, and EBR2, the access
requiring 3 cycles. Three cycles are required for a byte or word access to RAMER, and 6
cycles for a longword access.
When a longword write is performed on RAMER, 0 must always be written to the lower
word (address H'FFFF0C72). Operation is not guaranteed if a nonzero value is written.
1. In the on-chip ROM disabled modes (MCU modes 2, 3, and 4), a read will return H'00,
and writes are invalid. Writes are also disabled when the FWE bit is not set to 1 in
FLMCR1.
2. When a high level is input to the FWE pin, the initial value is H'80.
3. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in
FLMCR1 is not set, these registers are initialized to H'00.
Rev. 5.00 Sep 11, 2006 page 734 of 916
REJ09B0332-0500