SH7065 Datasheet, PDF (445/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
• PWM mode 2
PWM output is generated using one TGR register as the cycle register and the others as duty
registers. The output specified by TIOR is performed upon compare match. Upon counter
clearing by a cycle register compare match, the output value of each pin is the initial value set
in TIOR. If the set values of the cycle and duty registers are identical, the output value does not
change when a compare match occurs.
In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with
synchronous operation.
The correspondence between PWM output pins and registers is shown in table 10.7.
Table 10.7 PWM Output Registers and Output Pins
Output Pins
Channel
Registers
PWM Mode 1
PWM Mode 2
0
TGR0A
TIOC0A
TIOC0A
TGR0B
TIOC0B
TGR0C
TIOC0C
TIOC0C
TGR0D
TIOC0D
1
TGR1A
TIOC1A
TIOC1A
TGR1B
TIOC1B
2
TGR2A
TIOC2A
TIOC2A
TGR2B
TIOC2B
3
TGR3A
TIOC3A
TIOC3A
TGR3B
TIOC3B
TGR3C
TIOC3C
TIOC3C
TGR3D
TIOC3D
4
TGR4A
TIOC4A
TIOC4A
TGR4B
TIOC4B
5
TGR5A
TIOC5A
TIOC5A
TGR5B
TIOC5B
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set.
Rev. 5.00 Sep 11, 2006 page 423 of 916
REJ09B0332-0500