SH7065 Datasheet, PDF (402/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or
TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot
be modified.
Bit 4: BFA
0
1
Description
TGRA operates normally
TGRA and TGRC are used together for buffer operation
(Initial value)
Bit 3 to 0—Mode 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.
Bit 3: MD3^*1 Bit 2: MD2^*2 Bit 1: MD1
0
0
0
1
1
0
1
1
*
*
Legend:
*: Don’t care
Bit 0: MD0
0
1
0
1
0
1
0
1
*
Description
Normal operation
(Initial value)
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
—
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
2. Phase counting mode cannot be set for channels 0 and 3. In these channels, 0 should
always be written to MD2.
Rev. 5.00 Sep 11, 2006 page 380 of 916
REJ09B0332-0500