SH7065 Datasheet, PDF (456/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
TCLKA
TCLKB
Edge
detection
circuit
Channel 1
TCNT1
TGR1A
(speed period capture)
TGR1B
(position period capture)
TCNT0
TGR0A
+
(speed control period)
–
TGR0C
+
(position control period)
–
TGR0B
(pulse width capture)
TGR0D
(buffer operation)
Channel 0
Figure 10.32 Phase Counting Mode Application Example
10.5 Interrupts
10.5.1 Interrupt Sources and Priorities
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable
bit, allowing generation of internal reset signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, but the priority order within
a channel is fixed. For details, see section 6, Interrupt Controller (INTC).
Rev. 5.00 Sep 11, 2006 page 434 of 916
REJ09B0332-0500