SH7065 Datasheet, PDF (168/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
Bits 15 to 0:
MSTP31 to MSTP0
0
1
Description
Clock is supplied to corresponding module
Clock supply to corresponding module is stopped
(Initial value)
4.9.3 Module Clock Control Registers 1 to 5 (MCLKCR1 to MCLKCR5)
Module clock control registers 1 to 5 (MCLKCR1 to MCLKCR5) are 16-bit readable/writable
registers that specify the division ratio for the clocks supplied to the modules.
Registers MCLKCR1 to MCLKCR5 are initialized to a value determined by the clock mode in a
power-on reset, but are not initialized in software standby mode.
MCLKCR1
Bit: 15
14
13
12
11
10
9
8
—
MCLK MCLK MCLK
—
MCLK MCLK MCLK
032
031
030
022
021
020
Initial value:
1
—
—
—
1
—
—
—
R/W: R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
—
MCLK MCLK MCLK
—
MCLK MCLK MCLK
012
011
010
002
001
000
Initial value:
1
—
—
—
1
—
—
—
R/W: R
R/W
R/W
R/W
R
R/W
R/W
R/W
MCLKCR2
Bit: 15
14
13
12
11
10
9
8
—
MCLK MCLK MCLK
—
MCLK MCLK MCLK
072
071
070
062
061
060
Initial value:
1
—
—
—
1
—
—
—
R/W: R
R/W
R/W
R/W
R
R/W
R/W
R/W
Rev. 5.00 Sep 11, 2006 page 146 of 916
REJ09B0332-0500