SH7065 Datasheet, PDF (481/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.2 Register Descriptions
Section 11 Motor Management Timer (MMT)
11.2.1 Timer Mode Register (TMDR)
The timer mode register (TMDR) is an 8-bit readable/writable register that sets the operating mode
and selects the PWM output level.
TMDR is initialized to H'00 by a power-on reset and in standby mode. It is not initialized in
module standby mode.
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
OLSN OLSP MD1 MD0
Initial value:
0
0
0
0
0
0
0
0
R/W: —
—
—
—
R/W
R/W
R/W
R/W
Bits 7 to 4—Reserved: These bits are always read as 0 and should only be written with 0.
Bit 3—Output Level Select N (OLSN): Selects the negative phase output level in the operating
modes.
Bit 3: OLSN
0
1
Description
Active level is low
Active level is high
(Initial value)
Bit 2—Output Level Select P (OLSP): Selects the positive phase output level in the operating
modes.
Bit 2: OLSP
0
1
Description
Active level is low
Active level is high
(Initial value)
Rev. 5.00 Sep 11, 2006 page 459 of 916
REJ09B0332-0500