SH7065 Datasheet, PDF (97/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Instruction
LDS.L @Rm+,A0
LDS.L @Rm+,X0
LDS.L @Rm+,X1
LDS.L @Rm+,Y0
LDS.L @Rm+,Y1
NOP
RTE
SETRC Rm
SETRC #imm
SETT
SLEEP
STC
STC
STC
STC
STC
STC
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STS
STS
STS
SR,Rn
GBR,Rn
VBR,Rn
MOD,Rn
RE,Rn
RS,Rn
SR,@-Rn
GBR,@-Rn
VBR,@-Rn
MOD,@-Rn
RE,@-Rn
RS,@-Rn
MACH,Rn
MACL,Rn
PR,Rn
Instruction Code
Operation
Execution
States T Bit
0100mmmm01110110 (Rm) → A0, Rm + 4 → Rm 1
—
0100mmmm10000110 (Rm) → X0, Rm + 4 → Rm 1
—
0100mmmm10010110 (Rm) → X1, Rm + 4 → Rm 1
—
0100mmmm10100110 (Rm) → Y0, Rm + 4 → Rm 1
—
0100mmmm10110110 (Rm) → Y1, Rm + 4 → Rm 1
—
0000000000001001 No operation
1
—
0000000000101011 Delayed branch,
4
LSB
stack area → PC/SR
0100mmmm00010100 RE – RS operation result
1
—
(repeat status) → RF1, RF0
Rm [11:0] → RC (SR [27:16])
10000010iiiiiiii RE – RS operation result
1
1
(repeat status) → RF1, RF0
imm → RC (SR [23:16]),
zeros → SR [27:24]
0000000000011000 1 → T
0000000000011011 Sleep
1
1
3^*
—
0000nnnn00000010 SR → Rn
1
—
0000nnnn00010010 GBR → Rn
1
—
0000nnnn00100010 VBR → Rn
1
—
0000nnnn01010010 MOD → Rn
1
—
0000nnnn01110010 RE → Rn
1
—
0000nnnn01100010 RS → Rn
1
—
0100nnnn00000011 Rn – 4 → Rn, SR → (Rn)
2
—
0100nnnn00010011 Rn – 4 → Rn, GBR → (Rn) 2
—
0100nnnn00100011 Rn – 4 → Rn, VBR → (Rn) 2
—
0100nnnn01010011 Rn – 4 → Rn, MOD → (Rn) 2
—
0100nnnn01110011 Rn – 4 → Rn, RE → (Rn)
2
—
0100nnnn01100011 Rn – 4 → Rn, RS → (Rn)
2
—
0000nnnn00001010 MACH → Rn
1
—
0000nnnn00011010 MACL → Rn
1
—
0000nnnn00101010 PR → Rn
1
—
Rev. 5.00 Sep 11, 2006 page 75 of 916
REJ09B0332-0500