SH7065 Datasheet, PDF (119/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
2. Programming countermeasure
This restriction can be avoided by using any of methods (1) to (3) below.
(1) Do not execute an instruction sequence conforming to condition b. above in on-chip X/Y
memory.
(2) If an instruction sequence conforming to condition b. above is present in instruction code
and there is no problem if the order of instructions is changed, switch round instructions (2)
and (3).
(3) If an instruction sequence conforming to condition b. above is present in instruction code
and there is a problem with changing the order of instructions, insert one or more NOP
instructions, or CPU instructions unrelated to the multiplier, between instructions (1) and
(2).
Rev. 5.00 Sep 11, 2006 page 97 of 916
REJ09B0332-0500