SH7065 Datasheet, PDF (251/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
Bit 13—High-Impedance Control (HIZCNT): Specifies the state of the RAS, CAS, and OE
signals (which control the DRAM self-refresh status) in standby mode and when the bus is
released. This enables the DRAM to be kept in the self-refresh state.
Bit 13: HIZCNT
0
1
Description
The RAS, CAS, and OE signals go to the high-impedance (Hi-Z) state in
standby mode and when the bus is released
(Initial value)
The RAS, CAS, and OE signals drive in standby mode and when the bus is
released
Bits 12 to 0—Reserved: These bits are always read as 0 and should only be written with 0.
8.2.2 Area Control Registers 1 (ACR1_0 to ACR1_5)
The ACR1 registers are 16-bit readable/writable registers that specify the type of memory to be
connected to each area, acceptance of external waits, bus width, number of idle cycles, and
number of CS expansion cycles.
The ACR1 registers are initialized to H'07FF (ACR1_0 to ACR1_3 for areas 0 to 3) or H'0000
(ACR1_4 and ACR1_5 for areas 4 and 5) by a power-on reset, but are not initialized in standby
mode.
Registers ACR1_0 to ACR1_3 (forAreas 0 to 3)
Bit: 15
14
13
12
11
10
9
8
ENDIAN TP1
TP0 EXWE
—
SZ1
SZ0
IW2
Initial value:
0
0
0
0
0
1
1
1
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
IW1
Initial value:
1
R/W: R/W
6
5
4
3
2
1
0
IW0 SWH2 SWH1 SHW0 SWT2 SWT1 SWT0
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 Sep 11, 2006 page 229 of 916
REJ09B0332-0500