SH7065 Datasheet, PDF (129/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
The function of each of the CPG blocks is described below.
PLL Circuit 1: PLL circuit 1 has the function of multiplying the frequency of the clock from the
CKIO pin or PLL circuit 2 by a factor of 1 or 2. The phase of the rising edge of the external bus
clock (CKE) is controlled so that it matches the phase of the rising edge at the CKIO pin. The
multiplication factor is determined by the clock operating mode.
PLL Circuit 2: PLL circuit 2 has the function of multiplying the frequency of the input clock
from the crystal oscillator or EXTAL pin by a factor of 2 or 4. The multiplication factor is
determined by the clock operating mode.
Crystal Oscillator: This is the oscillator circuit used when a crystal resonator is connected to the
XTAL and EXTAL pins. Use of the crystal oscillator can be selected by a clock operating mode
setting,
Frequency Divider 1: Frequency divider 1 has the function of generating the master clock
(CKM). The master clock (CKM) operating frequency can be selected from 4, 2, 1, 1/2, or 1/4
times the input clock frequency according to the clock mode. The division ratio is set in the
frequency control register.
Frequency Divider 2: Frequency divider 2 has the function of generating the peripheral clock
(CKP). The peripheral clock (CKP) operating frequency can be selected from 4, 2, 1, 1/2, or 1/4
times the input clock frequency according to the clock mode. The division ratio is set in the
frequency control register.
Frequency Divider 3: Frequency divider 3 has the function of generating the external bus clock
(CKE). The external bus clock (CKE) operating frequency can be selected from 4, 2, 1, 1/2, or 1/4
times the input clock frequency according to the clock mode. The division ratio is set in the
frequency control register.
Frequency Divider 4: Frequency divider 4 has the function of generating external clock output
(CK). The external clock output (CK) operating frequency can be selected from 4, 2, 1, 1/2, or 1/4
times the input clock frequency according to the clock mode. The division ratio is set in the
frequency control register.
Clock Mode/Clock Output Control Circuit: The clock mode/clock output control circuit
controls the clock mode and the clock output from the CK/CKIO pin by means of the frequency
control register.
Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillator
circuit and other modules when the clock is switched and in sleep and standby modes.
Rev. 5.00 Sep 11, 2006 page 107 of 916
REJ09B0332-0500