SH7065 Datasheet, PDF (734/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 18 I/O Ports (I/O)
18.5.1 Register Configuration
The port D registers are shown in table 18.7.
Table 18.7 Port D Registers
Name
Port D data register H
Port D data register L
Abbreviation R/W
PDDRH
R/W
PDDRL
R/W
Initial Value
H'0000
H'0000
Address
H'FFFF 1230
H'FFFF 1232
Access Size
8, 16, 32
8, 16, 32
18.5.2 Port D Data Register H (PDDRH)
Bit: 15
14
13
12
11
10
9
8
PD31DR PD30DR PD29DR PD28DR PD27DR PD26DR PD25DR PD24DR
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
PD23DR PD22DR PD21DR PD20DR PD19DR PD18DR PD17DR PD16DR
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port D data register H (PDDRH) is a 16-bit readable/writable register that stores port D data. Bits
PD31DR to PD16DR correspond to pins PD31/D31/RXD2/TIOC5A to PD16/D16/POE0.
When a pin functions as a general output, if a value is written to PDDRH, that value is output
directly from the pin, and if PDDRH is read, the register value is returned directly regardless of
the pin state.
When a pin functions as a general input, if PDDRH is read the pin state, not the register value, is
returned directly. If a value is written to PDDRH, although that value is written into PDDRH it
does not affect the pin state. Table 18.8 summarizes port D data register read/write operations.
PDDRH is initialized by an external power-on reset, but is not initialized by a WDT reset or in
standby mode or sleep mode.
Rev. 5.00 Sep 11, 2006 page 712 of 916
REJ09B0332-0500