SH7065 Datasheet, PDF (779/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 19 256 kB Flash Memory (F-ZTAT)
BF
;
BRA
NOP
;
PROGRAM_OK
MOV
PROGRAM_END
MOV
MOV.B
;
MOV.L
WAIT_13 DT
BF
;
RTS
NOP
;
ADATABUFF
RDATABUFF
PROGRAM_END
PROGRAM_LOOP
.EQU $
#OK,R13
; Move OK (return value) to R13
.EQU $
#SWECLEAR,R0
; Clear SWE
R0,@(FLMCR1,GBR)
#WAIT_F,R2
R2
WAIT_13
; Wait 100 µs
.RES.B 128
.RES.B 128
; Additional programming RAM area
; Reprogramming RAM area
19.7.3 Erase Mode (n = 1 for Addresses H'00000 to H'07FFF, n = 2 for Addresses H'08000
to H'3FFFF)
When erasing flash memory, the erase/erase-verify flowchart (single-block erase) shown in figure
19.14 should be followed for each block.
To perform data or program erasure, set the flash memory area to be erased in erase block register
n (EBRn) at least 1 µs after setting the SWE bit to 1 in flash memory control register 1
(FLMCR1). Next, the watchdog timer is set to prevent overprogramming in the event of program
runaway, etc. After this, preparation for erase mode (erase setup) is carried out by setting the ESU
bit in FLMCR1, and after the elapse of 100 µs or more, the operating mode is switched to erase
mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory
erase time. Ensure that the erase time does not exceed 10 ms.
Note: With flash memory erasing, preprogramming (setting all memory data in the memory to
be erased to all “0”) is not necessary before starting the erase procedure.
Rev. 5.00 Sep 11, 2006 page 757 of 916
REJ09B0332-0500