SH7065 Datasheet, PDF (257/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
8.2.4 DRAM Control Register 1 (DCR1)
DRAM control register 1 (DCR1) is a 16-bit readable/writable register that specifies DRAM
control. Control is the same for CS4 and CS5 space accesses.
DCR1 is initialized to H'0000 by a power-on reset, but is not initialized in standby mode.
Bit:
Initial value:
R/W:
15
TPC1
0
R/W
14
TPC0
0
R/W
13
TPCS2
0
R/W
12
TPCS1
0
R/W
11
TPCS0
0
R/W
10
RCD2
0
R/W
9
RCD1
0
R/W
8
RCD0
0
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
DWW1 DWW0 DWR1 DWR0
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R/W
R/W
R/W
R/W
R
R
Bits 15 and 14—RAS Precharge Interval Specification (TPC1, TPC0): These bits specify, for
DRAM, the minimum number of cycles before RAS is asserted again after being negated.
Bit 15: TPC1
0
1
Bit 14: TPC0
0
1
0
1
Description
1 cycle
2 cycles
3 cycles
4 cycles
(Initial value)
Bits 13 to 11—RAS Precharge Interval Immediately after Self-Refreshing (TPCS2 to
TPCS0): These bits specify, for DRAM, the RAS precharge interval immediately after self-
refreshing.
Rev. 5.00 Sep 11, 2006 page 235 of 916
REJ09B0332-0500