SH7065 Datasheet, PDF (115/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Table 2.42 Logical Shift Operation Instructions
Instruction
PSHL Sx,Sy,Dz
DCT PSHL Sx,Sy,Dz
DCF PSHL Sx,Sy,Dz
PSHL #imm,Dz
Operation
Instruction Code
Execution
States DC Bit
If Sy ≥ 0, Sx<<Sy → Dz,
Dz lower word is cleared
If Sy < 0, Sx>>Sy → Dz,
Dz lower word is cleared
111110********** 1
10000001xxyyzzzz
Updated
If DC = 1 & Sy ≥ 0,
111110********** 1
—
Sx<<Sy → Dz,
Dz lower word is cleared
10000010xxyyzzzz
If DC = 1 & Sy < 0,
Sx>>Sy → Dz,
Dz lower word is cleared
If DC = 0, nop
If DC = 0 & Sy ≥ 0,
111110********** 1
—
Sx<<Sy → Dz,
Dz lower word is cleared
10000011xxyyzzzz
If DC = 0 & Sy < 0,
Sx>>Sy → Dz,
Dz lower word is cleared
If DC = 1, nop
If imm ≥ 0, Dz<<imm → Dz,
Dz lower word is cleared
If imm < 0, Dz>>imm → Dz,
Dz lower word is cleared
111110********** 1
00000iiiiiiizzzz
Updated
Rev. 5.00 Sep 11, 2006 page 93 of 916
REJ09B0332-0500