SH7065 Datasheet, PDF (809/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 20 256 kB Mask ROM
Section 20 256 kB Mask ROM
20.1 Overview
The SH7065 has 256 kbytes of on-chip mask ROM. The on-chip ROM is connected to the CPU
and direct memory access controller (DMAC) by a 32-bit-wide data bus (figure 20.1). The CPU
and DMAC can use 8-, 16-, or 32-bit access to the on-chip ROM.
The on-chip ROM is 64 bits wide, and is accessed in two cycles. It is connected to the internal
data bus (C-bus) via an on-chip ROM buffer, and has a basic access capability of 32 bits per cycle.
Internal data bus (32 bits)
Buffer unit
Internal ROM bus (64 bits)
H'00000000
H'00000004
H'00000001
H'00000005
H'00000002
H'00000006
H'00000003
H'00000007
On-chip ROM
H'0003FFFC H'0003FFFD H'0003FFFE
H'0003FFFF
Figure 20.1 Block Diagram of On-Chip ROM (256 KB Version)
The on-chip ROM is enabled or disabled depending on the operating mode. For details of the
operating modes, see section 3, Operating Modes. The mode is selected by mode setting pins MD3
to MD0, as shown in figure 20.1. Select mode 0 or 1 when on-chip ROM is used, and mode 2, 3,
or 4 when it is not used. The on-chip ROM is allocated to addresses H'00000000 to H'0003FFFF
(256 kB version) in memory area 0.
Rev. 5.00 Sep 11, 2006 page 787 of 916
REJ09B0332-0500