SH7065 Datasheet, PDF (91/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Table 2.21 Arithmetic Operation Instructions
Instruction
ADD
Rm,Rn
ADD
#imm,Rn
ADDC Rm,Rn
ADDV Rm,Rn
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PL Rn
CMP/PZ Rn
CMP/STR Rm,Rn
DIV1
Rm,Rn
DIV0S Rm,Rn
DIV0U
DMULS.L Rm,Rn
Instruction Code
Operation
Execution
States T Bit
0011nnnnmmmm1100 Rn + Rm → Rn
1
—
0111nnnniiiiiiii Rn + imm → Rn
1
—
0011nnnnmmmm1110 Rn + Rm + T → Rn,
1
carry → T
Carry
0011nnnnmmmm1111 Rn + Rm→ Rn,
1
overflow → T
Overflow
10001000iiiiiiii When R0 = imm,
1
1→T
Comparison
result
0011nnnnmmmm0000 When Rn = Rm,
1
1→T
Comparison
result
0011nnnnmmmm0010 When Rn ≥ Rm
1
(unsigned), 1 → T
Comparison
result
0011nnnnmmmm0011 When Rn ≥ Rm (signed), 1
1→T
Comparison
result
0011nnnnmmmm0110 When Rn > Rm
1
(unsigned), 1 → T
Comparison
result
0011nnnnmmmm0111 When Rn > Rm (signed), 1
1→T
Comparison
result
0100nnnn00010101 When Rn > 0, 1 → T 1
Comparison
result
0100nnnn00010001 When Rn ≥ 0, 1 → T 1
Comparison
result
0010nnnnmmmm1100 When any bytes are 1
equal, 1→ T
Comparison
result
0011nnnnmmmm0100 1-step division
1
Calculation
(Rn ÷ Rm)
result
0010nnnnmmmm0111 MSB of Rn → Q,
1
MSB of Rm → M,
M^Q → T
Calculation
result
0000000000011001 0 → M/Q/T
1
0
0011nnnnmmmm1101 Signed, Rn × Rm →
2–4^*
—
MACH, MACL
32 × 32 → 64 bits
Rev. 5.00 Sep 11, 2006 page 69 of 916
REJ09B0332-0500