SH7065 Datasheet, PDF (378/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
9.3.6 Parallel Operation of DMA and CPU
The SH7065 has two 32-bit internal buses, the C-bus and I-bus. DMA is never the master on the
C-bus, so the CPU can access mask ROM and on-chip flash memory from the C-bus during DMA
transfer. However, when the DMA controller is accessing X-RAM or Y-RAM, the CPU cannot
simultaneously access the same RAM.
The combinations of access spaces for which parallel DMA and CPU operation is possible are
shown in table 9.7.
9.3.7 DMA Transfer When External Bus Is Released
If the DMA transfer source and transfer destination are both on-chip memory or on-chip peripheral
modules, DMA transfer cannot be performed while the external bus is released. The combinations
of transfer source and transfer destination for which DMA transfer is possible while the external
bus is released are shpown in table 9.8.
Rev. 5.00 Sep 11, 2006 page 356 of 916
REJ09B0332-0500