SH7065 Datasheet, PDF (740/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 18 I/O Ports (I/O)
18.7.2 Port F Data Register L (PFDRL)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
PF7DR PF6DR PF5DR — PF3DR PF2DR PF1DR —
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R
R/W
R/W
R/W
R
Port F data register L (PFDRL) is a 16-bit readable/writable register that stores port F data. Bits
PF7DR to PF1DR correspond to pins PF7/DREQ1/IRQOUT/TIOC0D to PF1/DACK0/TIOC0B.
When a pin functions as a general output, if a value is written to PFDRL, that value is output
directly from the pin, and if PFDRL is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PFDRL is read the pin state, not the register value, is
returned directly. If a value is written to PFDRL, although that value is written into PFDRL it does
not affect the pin state. Table 18.12 summarizes port F data register read/write operations.
PFDRL is initialized by an external power-on reset, but is not initialized by a WDT reset or in
standby mode or sleep mode.
Table 18.12 Port F Data Register (PFDR) Read/Write Operations
PFIOR
0
1
Pin Function
General input
Read
Pin state
Other than general
input
General output
Other than general
output
Undefined
PFDR value
PFDR value
Write
Value is written to PFDR, but does not
affect pin state
Value is written to PFDR, but does not
affect pin state
Write value is output from pin
Value is written to PFDR, but does not
affect pin state
Rev. 5.00 Sep 11, 2006 page 718 of 916
REJ09B0332-0500