SH7065 Datasheet, PDF (820/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 22 Electrical Characteristics
22.3.2 Control Signal Timing
Table 22.5 Control Signal Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC = 5.0 V ±0.5 V/3.3 V ±0.3 V, PV_CC ≥ V_CC,
AV_CC = 3.3 V ±0.3 V, V_SS = PLLV_SS = PV_SS = AV_SS = 0 V, Ta = –20°C to +75°C
Item
RES rise and fall
RES pulse width
NMI rise and fall
NMI pulse width
IRQ pulse width
IRQOUT output delay time
Bus request setup time
Bus acknowledge delay time 1
Bus acknowledge delay time 2
Bus three-state delay time
Notes: 1. Slowest module clock
2. Slower of Mφ and CKE clocks
Symbol Min
tRESr, tRESf —
tRESW
40
tNMIr, tNMIf —
tNMIW
2.5
tIRQW
2.5
tIRQOD
—
tBRQS
35
tBACKD1
—
tBACKD2
—
tBZD
—
Max
200
—
200
—
—
35
—
35
35
35
Unit
ns
tcyc^*1
ns
tcyc^*2
tcyc^*2
ns
ns
ns
ns
ns
Figure
Figure 22.5
Figure 22.6
Figure 22.7
Figure 22.8
CKM
RES
t_RESf
t_RESr
V_IH
V_IL
t_RESW
V_IH
V_IL
Figure 22.5 Reset Input Timing
Rev. 5.00 Sep 11, 2006 page 798 of 916
REJ09B0332-0500