SH7065 Datasheet, PDF (772/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 19 256 kB Flash Memory (F-ZTAT)
Write pulse application subroutine
Sub-routine write pulse
Enable WDT
Set PSU bit in FLMCR1
Wait 50 µs
Set P bit in FLMCR1
Wait 10 µs, 30 µs, or 200 µs
*5
Clear P bit in FLMCR1
Wait 5 µs
Clear PSU bit in FLMCR1
Wait 5 µs
Disable WDT
End sub
Start of programming
Start
Set SWE bit in FLMCR1
Wait 1 µs
Store 128-byte program data in program
data area and reprogram data area
n=1
Programming must be executed in the erased
state. Do not perform additional programming
on addresses that have already been
programmed.
*4
m=0
Write 128-byte data in reprogram data area
in RAM consecutively to flash memory
*1
Sub-routine-call
Write pulse
30 µs or 200 µs
See Note 6 for pulse width
Set PV bit in FLMCR1
Wait 4 µs
H'FF dummy write to verify address
Increment address
Wait 2 µs
Read verify data
*2
n←n+1
Note: *6: Write Pulse Width
Number of Writes n Write Time (z) (µsec)
1
30
2
30
3
30
4
30
5
30
6
30
7
200
8
200
9
200
10
200
11
200
12
200
1...3
20... 0
998
200
999
200
1000
200
Note: Use a 10 µs write pulse for additional
programming.
RAM
Program data storage
area (128 bytes)
Program data =
NG
verify data?
OK
6 ≥ n?
NG
OK
Additional program data computation
m=1
Transfer additional program data
to additional program data area
*4
Reprogram data computation
*3
Transfer reprogram data to reprogram data area *4
128-byte data verification
NG
completed?
OK
Clear PV bit in FLMCR1
Wait 2 µs
6 ≥ n?
NG
OK
Write 128-byte data in additional program data
area in RAM consecutively to flash memory
*1
Reprogram data storage
area (128 bytes)
Additional program data
storage area (128 kbytes)
Additional write pulse 10 µs
NG
m = 0?
OK
Clear SWE bit in FLMCR1
n ≥ 1000?
NG
OK
Clear SWE bit in FLMCR1
Wait 100 µs
Wait 100 µs
End of programming
Programming failure
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even
if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 32-bit (longword) units.
3. Even bits for which programming has been completed in the 128-byte programming loop will be subjected to additional programming if they fail the subsequent
verify operation.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data must be provided in
RAM. The reprogram and additional program data contents are modified as programming proceeds.
5. The write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See Note *6 for the pulse widths. When writing of additional
program data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
Reprogram Data Computation Chart
Original Data (D)
Verify Data (V)
0
0
1
1
0
1
Reprogram Data (X)
1
0
1
1
Comments
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Additional Program Data Computation Chart
Reprogram Data (X') Verify Data (V) Additional Program Data (Y)
Comments
0
0
0
Additional programming executed
1
1
Additional programming not executed
1
0
1
Additional programming not executed
1
1
Additional programming not executed
Figure 19.13 Program/Program-Verify Flowchart
Rev. 5.00 Sep 11, 2006 page 750 of 916
REJ09B0332-0500