SH7065 Datasheet, PDF (518/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 12 Compare Match Timer (CMT)
12.2 Register Descriptions
12.2.1 Compare Match Timer Start Register (CMSTR)
The compare match timer start register (CMSTR) is a 16-bit register that specifies operation or
stoppage of the counters (CMCNT) in channels 0 and 1.
CMSTR is initialized by a power-on reset, and in hardware standby mode and software standby
mode. It is not initialized in module standby mode.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
STR1 STR0
Initial value:
0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
R/W
R/W
Bits 15 to 2—Reserved: These bits are always read as 0 and cannot be modified.
Bit 1—Count Start 1 (STR1): Selects operation or stoppage of compare match timer counter 1.
Bit 1: STR1
0
1
Description
CMCNT1 count operation is stopped
CMCNT1 performs count operation
(Initial value)
Bit 0—Count Start 0 (STR0): Selects operation or stoppage of compare match timer counter 0.
Bit 0: STR0
0
1
Description
CMCNT0 count operation is stopped
CMCNT0 performs count operation
(Initial value)
Rev. 5.00 Sep 11, 2006 page 496 of 916
REJ09B0332-0500