SH7065 Datasheet, PDF (506/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 11 Motor Management Timer (MMT)
Pay Attention to the Notices Below, When a Value Is Written into the Timer General
Register U (TGRU), Timer General Register V (TGRV), Timer General Register W
(TGRW), and in Case of Written into Free Operation Address (*):
• In case of counting up: Do not write a value {Previous value of TGRU + Td} into TGRU.
• In case of counting down: Do not write a value {Previous value of TGRU – Td} into TGRU.
In the same manner to TGRV and TGRW. When a value {Previous value of TGRU + Td} is
written (in case of counting down {Previous value of TGRU – Td}), the output of PUOA/PUOB,
PVOA/PVOB, PWOA/PWOB (corresponding to U, V, W phase) may not be output for 1 cycle.
Figure 11.17 shows the error case. When writing into the buffer operation address, these notes are
not relevant.
Note: * When addresses, H'FFFF049C, H'FFFF04AC, H'FFFF04BC are used as register
address for TBRU, TBRV, TBRW, respectively.
TGRU
Td
Previous TGRU
Previous TGRU
Td
TGRU
2Td
2Td
Count-up
Count down
Figure 11.17 Writing into Timer General Registers (When One Cycle Is Not Output)
Writing Operation into Timer Period Data Register (TPDR) and Timer Dead Time Data
Register (TDDR) When MMT Is Operating:
• Do not revise TPDR register when MMT is operating. Always use a buffer-write operation
through TPBR register.
• Do not revise TDDR register once an operation of MMT is invoked. When TDDR is revised, a
wave may not be output for as much as 1 cycle (full count period of 16 bits in TDCNT),
because a value cannot be written into TDCNT, which is compared to a value set in TDDR.
Rev. 5.00 Sep 11, 2006 page 484 of 916
REJ09B0332-0500