SH7065 Datasheet, PDF (172/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
higher than the interrupt mask level set in the CPU’s status register (SR), or when an interrupt
from an on-chip peripheral module is disabled on the module side.
Exit by DMAC Address Error: When a DMAC address error occurs, sleep mode is exited and
DMAC address error exception handling is executed.
Exit by Power-On Reset: When the RES pin is driven low, the SH7065 enters the power-on reset
state and exits sleep mode.
Exit by HSTBY Pin: When the HSTBY pin is driven low, the SH7065 enters the hardware
standby mode state and exits sleep mode.
4.11 Software Standby Mode
4.11.1 Transition to Software Standby Mode
If a SLEEP instruction is executed when the SBY bit in SBYCR is set to 1, the chip switches from
the program execution state to software standby mode. In software standby mode, the clock and
on-chip peripheral modules halt as well as the CPU, reducing power consumption to an extremely
low level. Clock output from the CKIO and CK pins is also stopped.
CPU register contents and data in on-chip RAM are retained. Some on-chip peripheral module
registers are initialized. The state of the peripheral module registers in software standby mode is
shown in table 4.15. See appendix B, Pin States, for the pin states.
The CPU regards the SBYCR write as being executed in one cycle, and performs the next
processing. However, the write actually takes the number of cycles shown in table 8.12 in section
8, Bus State Controller (BSC). To ensure that the value written from the CPU to SBYCR is
reliably reflected in the SLEEP instruction, either read SBYCR or else wait for the number of
cycles shown in table 8.12, before executing the SLEEP instruction.
In the software standby state, external bus address/data/bus control signals (except DRAM signals)
go to the high-impedance state, i.e. the bus-released state. In the software standby state, the BREQ
bus release request input signal is ignored. Note that the following two cases apply to the BACK
bus use enable output signal.
1. Transition from bus-released state (BREQ input asserted low) to software standby state
When the bus release request signal (BREQ) is asserted low in the normal state, the BACK pin
is set to low output, indicating that the bus has been released. If the software standby state is
entered in this state, BACK output goes high, but other address, data, and bus control signals
remain in the high-impedance state, i.e. the bus-released state. If the software standby state is
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REJ09B0332-0500