SH7065 Datasheet, PDF (484/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 11 Motor Management Timer (MMT)
11.2.3 Timer Status Register (TSR)
The timer status register (TSR) is an 8-bit register containing status flags.
TSR is initialized to H'80 by a power-on reset and in standby mode. It is not initialized in module
standby mode.
Bit: 7
6
5
4
3
2
1
0
TCFD
—
—
—
—
—
TGFN TGFM
Initial value:
1
0
0
0
0
0
0
0
R/W: R
—
—
—
—
—
R/(W)^* R/(W)^*
Note: * Can only be written with 0 for flag clearing.
Bit 7—Count Direction Flag (TCFD): Status flag that indicates the count direction of the TCNT
counter.
Bit 7: TCFD
0
1
Description
TCNT counts down
TCNT counts up
(Initial value)
Bits 6 to 2—Reserved: These bits are always read as 0 and should only be written with 0.
Bit 1—Output Compare Flag N (TGFN): Status flag that indicates the occurrence of a compare
match between TCNT and 2Td (Td: TDDR value).
Bit 1: TGFN
0
1
Description
[Clearing condition]
When 0 is written to TGFN after reading TGFN = 1
[Setting condition]
When TCNT = 2Td
(Initial value)
Rev. 5.00 Sep 11, 2006 page 462 of 916
REJ09B0332-0500