SH7065 Datasheet, PDF (229/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 7 User Break Controller (UBC)
7.2.2 User Break Address Mask Register (UBAMR)
UBAMRH
Bit:
Initial value:
R/W:
15
UBM31
0
R/W
14
UBM30
0
R/W
13
UBM29
0
R/W
12
UBM28
0
R/W
11
UBM27
0
R/W
10
UBM26
0
R/W
9
UBM25
0
R/W
8
UBM24
0
R/W
Bit:
Initial value:
R/W:
7
UBM23
0
R/W
6
UBM22
0
R/W
5
UBM21
0
R/W
4
UBM20
0
R/W
3
UBM19
0
R/W
2
UBM18
0
R/W
1
UBM17
0
R/W
0
UBM16
0
R/W
UBAMRL
Bit:
Initial value:
R/W:
15
UBM15
0
R/W
14
UBM14
0
R/W
13
UBM13
0
R/W
12
UBM12
0
R/W
11
UBM11
0
R/W
10
UBM10
0
R/W
9
UBM9
0
R/W
8
UBM8
0
R/W
Bit:
Initial value:
R/W:
7
UBM7
0
R/W
6
UBM6
0
R/W
5
UBM5
0
R/W
4
UBM4
0
R/W
3
UBM3
0
R/W
2
UBM2
0
R/W
1
UBM1
0
R/W
0
UBM0
0
R/W
The user break address mask register (UBAMR) consists of two 16-bit readable/writable registers:
user break address mask register H (UBAMRH) and user break mask address register L
(UBAMRL).
Control bits XYE and XYS in the user break bus cycle register (UBBR) select the break condition
address bus. When XYE is 0, UBAR specifies a break address on the CAB internal address bus or
IAB internal address bus. In this case, UBAMRH specifies which bits of the break address set in
UBARH are to be masked, and UBAMRL specifies which bits of the break address set in UBARL
are to be masked. When XYE is 1, UBAMRH specifies which bits of the break address on XAB
(bits 15 to 1) set in UBARH are to be masked, and UBAMRL specifies which bits of the break
address on YAB (bits 15 to 1) set in UBARL are to be masked. As XAB and YAB have only 15
Rev. 5.00 Sep 11, 2006 page 207 of 916
REJ09B0332-0500