SH7065 Datasheet, PDF (90/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Instruction
MOV.W Rm,@(R0,Rn)
MOV.L Rm,@(R0,Rn)
MOV.B @(R0,Rm),Rn
Instruction Code
0000nnnnmmmm0101
0000nnnnmmmm0110
0000nnnnmmmm1100
MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
@(R0,Rm),Rn 0000nnnnmmmm1110
R0,@(disp,GBR) 11000000dddddddd
R0,@(disp,GBR) 11000001dddddddd
R0,@(disp,GBR) 11000010dddddddd
@(disp,GBR),R0 11000100dddddddd
MOV.W @(disp,GBR),R0 11000101dddddddd
MOV.L @(disp,GBR),R0 11000110dddddddd
MOVA @(disp,PC),R0 11000111dddddddd
MOVT Rn
0000nnnn00101001
SWAP.B Rm,Rn
0110nnnnmmmm1000
SWAP.W Rm,Rn
0110nnnnmmmm1001
XTRCT Rm,Rn
0010nnnnmmmm1101
Operation
Rm → (R0 + Rn)
Rm → (R0 + Rn)
(R0 + Rm) → sign
extension → Rn
(R0 + Rm) → sign
extension → Rn
(R0 + Rm) → Rn
R0 → (disp + GBR)
R0 → (disp × 2 + GBR)
R0 → (disp × 4 + GBR)
(disp + GBR) → sign
extension → R0
(disp × 2 + GBR) → sign
extension → R0
(disp × 4 + GBR) → R0
disp × 4 + PC → R0
T → Rn
Rm → swap lower
2 bytes → Rn
Rm → swap upper/lower
words → Rn
Middle 32 bits of Rm and
Rn → Rn
Execution
States T Bit
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
Rev. 5.00 Sep 11, 2006 page 68 of 916
REJ09B0332-0500