SH7065 Datasheet, PDF (504/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 11 Motor Management Timer (MMT)
11.6 Usage Notes
Note that the kinds of operation and contention described below occur during MMT operation.
Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a buffer register (TBRU, TBRV, TBRW, or TPBR)
write cycle, data is transferred from the buffer register to the compare register (TGR or TPDR) by
means of a buffer operation. The data transferred is the buffer register write data.
Figure 11.15 shows the timing in this case.
Pφ
Address
Buffer register
write cycle
T1 T2
Buffer register
address
Write signal
Compare match
signal
Interrupt request
signal
Buffer register
Buffer register write data
N
M
Compare register
M
Figure 11.15 Contention between Buffer Register Write and Compare Match
Rev. 5.00 Sep 11, 2006 page 482 of 916
REJ09B0332-0500