SH7065 Datasheet, PDF (227/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 7 User Break Controller (UBC)
7.1.3 Register Configuration
The UBC has the five registers shown in table 7.1. These registers are used to set the break
conditions.
Table 7.1 UBC Registers
Name
Abbre-
viation
R/W
User break address register H
UBARH R/W
User break address register L
UBARL R/W
User break address mask register H UBAMRH R/W
User break address mask register L UBAMRL R/W
User break bus cycle register
UBBR
R/W
Initial
Value
H'0000
H'0000
H'0000
H'0000
H'0000
Address
H'FFFF0C80
H'FFFF0C82
H'FFFF0C84
H'FFFF0C86
H'FFFF0C88
Access
Size
16, 32
16, 32
16, 32
16, 32
16, 32
7.2 Register Descriptions
7.2.1 User Break Address Register (UBAR)
UBARH
Bit:
Initial value:
R/W:
15
UBA31
0
R/W
14
UBA30
0
R/W
13
UBA29
0
R/W
12
UBA28
0
R/W
11
UBA27
0
R/W
10
UBA26
0
R/W
9
UBA25
0
R/W
8
UBA24
0
R/W
Bit:
Initial value:
R/W:
7
UBA23
0
R/W
6
UBA22
0
R/W
5
UBA21
0
R/W
4
UBA20
0
R/W
3
UBA19
0
R/W
2
UBA18
0
R/W
1
UBA17
0
R/W
0
UBA16
0
R/W
Rev. 5.00 Sep 11, 2006 page 205 of 916
REJ09B0332-0500