SH7065 Datasheet, PDF (213/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 6 Interrupt Controller (INTC)
Bit 8—NMI Edge Select (NMIE): Specifies whether an interrupt request is detected at the falling
or rising edge of NMI input.
Bit 8: NMIE
0
1
Description
Interrupt request detected at falling edge of NMI input
Interrupt request detected at rising edge of NMI input
(Initial value)
Bits 7 to 0—Reserved: These bits are always read as 0 and cannot be modified.
6.3.3 Interrupt Control Register 2 (ICR2)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
Bit:
Initial value:
R/W:
7
IRQ7S
0
R/W
6
IRQ6S
0
R/W
5
IRQ5S
0
R/W
4
IRQ4S
0
R/W
3
IRQ3S
0
R/W
2
IRQ2S
0
R/W
1
IRQ1S
0
R/W
0
IRQ0S
0
R/W
Interrupt control register 2 (ICR2) is a 16-bit register that sets the input signal detection mode for
IRQ7 to IRQ0.
ICR2 is initialized to H'0000 by a power-on reset. It is not initialized in standby mode.
Bits 15 to 8—Reserved: These bits are always read as 0 and cannot be modified.
Bits 7 to 0—IRQ7 to IRQ0 Sense Select (IRQ7S to IRQ0S): These bits set the IRQ detection
mode for IRQ7 to IRQ0 interrupt requests.
Bits 7 to 0:
IRQ7S to IRQ0S
0
1
Description
Interrupt request detected at low level of IRQ input
Interrupt request detected at falling edge of IRQ input
(Initial value)
Rev. 5.00 Sep 11, 2006 page 191 of 916
REJ09B0332-0500