SH7065 Datasheet, PDF (27/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 1 Overview
Item
Direct memory
access controller
(DMAC)
(4 channels)
Timer pulse unit
(TPU)
(6 channels)
Motor
management
timer (MMT)
(1 channel)
Specifications
• DMA transfer possible for the following devices:
 External memory, external I/O, on-chip supporting modules (excluding
DMAC, BSC, UBC)
• DMA transfer requests by external pins (for two channels) and on-chip
peripheral modules, plus auto-request
• Cycle steal or burst transfer
• Relative channel priorities can be set
• Selection of dual or single address mode transfer
• Chain mode transfer possible
• Transfer data width: 8/16/32 bits
• 4-Gbyte address space, maximum 4G (4,294,967,296) transfers
• TEND output can be asserted for each channel at the end of DMA transfer
• Maximum 16 kinds of waveform output or maximum 16 kinds of
input/output processing based on six 16-bit timer channels
• 16 dual-function output compare registers/input capture registers
• Total of 16 independent comparators
• Selection of eight counter input clocks
• Input capture function
• Pulse output modes
 One-shot, toggle, PWM
• Phase counting mode
 Two-phase encoder count processing capability
• Non-overlap waveform output for 6-phase inverter control
• Dead times generated by dead time counters
• Any PWM duty from 0% to 100% can be set
• Toggle output possible in synchronization with PWM cycle
• Data transfer can be performed by DMAC activation
• A/D converter conversion start trigger can be generated
• Output-off functions
Rev. 5.00 Sep 11, 2006 page 5 of 916
REJ09B0332-0500