SH7065 Datasheet, PDF (174/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
4.11.2 Exit from Software Standby Mode
Software standby mode is exited by means of a power-on reset or the HSTBY pin.
Exit by NMI Interrupt: When a falling edge or rising edge (as selected with the NMI edge select
bit (NMIE) in interrupt control register 1 (ICR1) of the interrupt controller (INTC)) is detected in
the NMI signal, clock oscillation is started. This clock is supplied only to the watchdog timer
(WDT). When the time set in the clock select bits (CKS2 to CKS0) in the WDT’s timer
control/status register (TCSR) before entering software standby mode has elapsed, WDT overflow
occurs. This overflow is taken as an indication that the clock has settled, and the clock is then
supplied to the entire chip. Software standby mode is thus exited and NMI exception handling is
begun.
When exiting software standby mode by means of an NMI interrupt, set bit CKS2 to CKS0 so that
the WDT overflow period is at least as long as the oscillation settling time.
When exiting software standby mode with the NMI pin designated for falling edge detection,
ensure that the NMI pin level goes high when software standby mode is entered (when the clock is
stopped) and low when recovering from software standby mode (when the clock is restarted after
the oscillation settling time). When exiting software standby mode with the NMI pin designated
for rising edge detection, ensure that the NMI pin level goes low when software standby mode is
entered (when the clock is stopped) and high when recovering from software standby mode (when
the clock is restarted after the oscillation settling time).
Exit by Power-On Reset: When the RES pin is driven low, the SH7065 enters the power-on reset
state and exits software standby mode. The RES pin must be held low until clock oscillation
settles.
Exit by HSTBY Pin: When the HSTBY pin is driven low, the SH7065 enters the hardware
standby mode state and exits software standby mode.
Rev. 5.00 Sep 11, 2006 page 152 of 916
REJ09B0332-0500