SH7065 Datasheet, PDF (43/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Section 2 CPU
2.1 Register Configuration
The SH7065 has sixteen 32-bit general registers, six 32-bit control registers, and ten 32-bit system
registers.
As the SH7065 is upward-compatible with the SH-1 and SH-2 at the object code level, a number
of registers have been added to those provided in previous SuperH microcomputers. The additions
comprise three control registers (the repeat start register (RS), repeat end register (RE), and
modulo register (MOD)), one system register (the DSP status register (DSR)), and six registers
(A0, A1, X0, X1, Y0, and Y1) within the DSP data registers.
With SuperH microcomputer type instructions, general registers are used in the same way as in the
SH-1 and SH-2, but with DSP type instructions, general registers are used as address and index
registers for accessing memory.
2.1.1 General Registers
There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are
used for data processing and address calculation.
With SuperH microcomputer type instructions, R0 is used as an index register. With a number of
instructions, R0 is the only register that can be used. R15 is used as the stack pointer (SP). In
exception handling, R15 is used to reference the stack when saving and restoring the status register
(SR) and program counter (PC).
With DSP type instructions, eight of the sixteen general registers are used for addressing of X and
Y data memory and data memory (single data) that uses the I-bus.
To access X memory, R4 and R5 are used as X address register [Ax] and R8 is used as X index
register [Ix]. To access Y memory, R6 and R7 are used as Y address register [Ay] and R9 is used
as Y index register [Iy]. To access single data that uses the I-bus, R2, R3, R4, and R5 are used as
single data address register [As] and R8 is used as single data index register [Is].
DSP type instructions can access can access X and Y data memory simultaneously. Two sets of
address pointers are provided to specify the X and Y data memory addresses.
The general registers are shown in figure 2.1.
Rev. 5.00 Sep 11, 2006 page 21 of 916
REJ09B0332-0500