SH7065 Datasheet, PDF (523/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

12.4 Interrupts
Section 12 Compare Match Timer (CMT)
12.4.1 Interrupt Sources
The CMT has a compare match interrupt for each channel, each assigned a different vector
address. When interrupt request flag CMF is set to 1, and of interrupt enable bit CMIE is also 1,
the corresponding interrupt request is output.
When a CPU interrupt is initiated by an interrupt request, the relative channel priorities can be
changed by means of an interrupt controller setting. For details, see section 6, Interrupt Controller
(INTC).
12.4.2 Timing of Compare Match Flag Setting
The CMF bit is CMCSR is set to 1 by a compare match signal generated when the CMCOR and
CMCNT values match. The compare match signal is generated in the last state in which the match
is true (when the value at which the CMCNT match occurred is about to be updated). Therefore,
after a match between CMCNT and CMCOR, the compare match signal is not generated until the
next CMCNT counter input clock pulse.
Figure 12.4 shows the timing of CMF bit setting.
Pφ
CMCNT input clock
CMCNT
N
0
CMCOR
N
Compare match signal
CMF
CMI0, 1
Figure 12.4 Timing of CMF Setting
Rev. 5.00 Sep 11, 2006 page 501 of 916
REJ09B0332-0500