SH7065 Datasheet, PDF (355/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
Transfer Request
Channel Waiting
DMAC Operation
1. Issued for channels
0 and 3
3. Issued for channel 1
2. Start of channel 0
transfer
3
Channel Priority
Order
0>1>2>3
Change of
priority order
1, 3
4. End of channel 0
1>2>3>0
transfer
5. Start of channel 1
transfer
Change of
3
6. End of channel 1 ^{priority order} _{2 > 3 > 0 > 1}
transfer
7. Start of channel 3
transfer
None
8. End of channel 3
transfer
Change of
priority order
0>1>2>3
Figure 9.4 Example of Changes in Channel Priority Order in Round Robin Mode
Rev. 5.00 Sep 11, 2006 page 333 of 916
REJ09B0332-0500